RISC-V grows open source processor membership 130% in 2021

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RISC-V International said it has grown during the pandemic as its RISC-V open source processor membership popped 130% in 2021.

The nonprofit group’s membership has grown from a ragtag group of feisty academics to some of the biggest tech companies on earth like Google. Over the past decade, the group has groomed RISC-V into a viable alternative to proprietary Arm and Intel-based processors, and it appears that a lot of big companies and engineering geeks like what they see.

RISC-V chip revenues are expected to generate $400 million in 2021 and reach $1 billion in revenue by 2024, according to a prediction made this week by accounting and consulting firm Deloitte. The firm said the ripples of RISC-V could turn into the waves of the future. Calista Redmond, CEO of RISC-V International, said in an interview with VentureBeat that there are 2,4278 members in the group now, up 130% since the start of the year, and 292 companies, up 27.5% this year.

“We’ve increased and grown and we have seen a deeper investment coming in from around the world, as you see that the reflection in our board composition, which is both premier members who are coming in at our highest level of membership, as well as elected representatives of various groups,” Redmond said. “That deeper investment is a reflection of them bringing RISC-V across their portfolio of products rather than just isolated to a few projects.”

The RISC-V membership will be gathering in San Francisco both in-person and online at an event anchored at the Moscone convention center. The members are announcing today that they have ratified 15 new specifications — representing more than 40 extensions to the hardware architecture — for the RISC-V instruction set architecture, which anyone can use for free.

Image Credit: RISC-V Foundation

Redmond said one of the benefits of RISC-V is that it is sanction-free. As an open source platform, RISC-V is not affected by export restrictions. This makes it appealing to companies, especially in China, that have been affected or fear being affected by those restrictions, Deloitte said. Redmond said that the nonprofit had to reboot its entire membership base as it transferred its headquarters from the U.S. to Switzerland in order to erase any doubt that it was independent of geographic borders.

Deloitte said that companies are planning on using it for different storage, graphics, and machine-learning applications. Even Intel’s foundry services division is partnering with RISC-V player SiFive. Arm argues that it has more features and has more support options for developers. Since Arm is based in the United Kingdom and Intel in the U.S., Chinese manufacturers worry that they could lose access to the architectures if trade friction heats up. Nvidia is hoping regulators will approve its plan to pay $40 billion to buy Arm.

Redmond said there are a lot of Chinese members, but overall RISC-V’s base is about a third North America, a third European, and a third Asian.

“We’ve always been global. There is nothing that changed at all in the rules, regulations, or global constructs that we participate in,” Redmond said. “Our move was primarily just to address any concerns that the landscape could change.”

Redmond said that designers don’t have to worry about constraints on what they do and that gives them freedom for innovation.

Deloitte also said that startups care about the royalty-free open source architecture. In the three years between 2020 and 2022, venture capitalists (VCs) will invest about $22 billion into startup chip companies of all kinds, Deloitte said. A million-dollar license fee may not matter to one of the world’s largest smartphone companies, but it does matter for a startup that has relatively little cash and a monthly burn rate, Deloitte said.

The served addressable market (SAM) for RISC-V in automotive alone was 4 million cores in 2020, forecast to rise to 150 million cores in 2022, and to 2.9 billion cores by 2025.

New specifications

risc v software

Image Credit: Tractica

Mark Himelstein, chief technology officer of RISC-V International, said in an interview with VentureBeat that the specifications cover vector, scalar cryptography, and hypervisor features that will keep extending the reach of RISC-V processors into new markets. Developers will find it easier to create RISC-V applications for artificial intelligence (AI) and machine learning (ML), the Internet of Things (IoT), connected and autonomous cars, data centers, and more, he said.

“The development of these specifications really showcased the incredible benefits of open collaboration across companies and geographies as members worked together to develop novel approaches for the latest computing requirements,” said Krste Asanović, chair of the RISC-V International, in a statement.

Redmond and Himelstein said that RISC-V’s advantages include that designs based on it are easy to modify. As such, they can offer greater flexibility than traditional chip designs.

“All 15 of those specifications have been ratified by the board. They all have passed acceptance criteria. And we’re very excited about that,” Himelstein said. “And we have another bunch on deck.”

The RISC-V Vector specification will help accelerate the computation of data intensive operations like ML inference for audio, vision, and voice processing. With RISC-V Vector, developers can process complex data arrays and scalar operations quickly and with low latency. The simplicity and flexibility of Vector allows companies to easily customize RISC-V solutions for a wide variety of edge computing applications from consumer IoT devices to industrial ML applications.

“The new RISC-V Vector specification will change the way people think about vector designs,” said Dave Ditzel, executive chairman of Esperanto Technologies, in a statement. “With just over 100 instructions, the extension offers a simple and elegant approach to efficiently process the latest machine learning algorithms.”

The RISC-V Hypervisor specification virtualizes supervisor-level architecture to efficiently host guest operating systems atop a type-1 or type-2 hypervisor. Virtual machine implementations require the RISC-V Hypervisor specification. The Hypervisor specification will help drive RISC-V adoption in cloud and embedded applications where virtualization is critical, such as in data centers, automotive applications, and industrial control applications. The RISC-V community has ported KVM and other open source virtual machines on top of simulators using the new specification.

The RISC-V Scalar Cryptography specification enables the acceleration of cryptographic workloads for small footprint deployments. These extensions significantly lower the barrier to entry for secure and efficient accelerated cryptography in IoT and embedded devices.

“The RISC-V Scalar Cryptography extensions allow for implementing standard cryptographic hash and block cipher algorithms that are an order of magnitude faster than using standard instructions in some cases. With RISC-V’s transparent and open approach, anyone can efficiently implement critical cryptographic algorithms in any class of CPU,” said Ben Marshall, cryptographic hardware engineer at PQShield and member of the RISC-V Technical Steering Committee, in a statement. “In addition to the performance benefits, these new extensions are very cheap to implement so companies can integrate popular cryptography algorithms in even the smallest connected devices.”

Originally appeared on: TheSpuzz