Intel researchers claim to be two years ahead with breakthrough PowerVia tech

Intel researchers claim to be a year ahead with a breakthrough power technology for chips dubbed PowerVia.

The big chipmaker announced PowerVia today as a key part of its technology for balancing performance and power efficiency for the next cycle of Moore’s Law. Intel expects to launch the tech in 2024 with its leading processors, and it says the solution has numerous benefits. This solves growing interconnection/wiring bottlenecks as tasks such as AI processing become more demanding.

A test chip has shown that PowerVia delivers 90% cell utilization, making a chip’s design less costly. Intel also said the test also showed more than 30% platform voltage droop improvement and 6% frequency benefit — factors that will help performance and power efficiency.

“From everything we’ve seen, others will follow to reap the same gains that we see,” said Intel vice president of technology Ben Sell said in a press briefing.

Intel said it is the first in the industry to implement backside power delivery on a product-like test chip, achieving the performance needed to propel the world into the next era of computing. PowerVia, which will be introduced on the Intel 20A manufacturing process node in the first half of 2024, is Intel’s industry-leading backside power delivery solution. It solves the growing issue of interconnect bottlenecks in area scaling by moving power routing to the backside of a wafer.

“PowerVia is a major milestone in our aggressive ‘five nodes in four years’ strategy and on our path to achieving a trillion transistors in a package in 2030,” Sell said. “Using a trial process node and subsequent test chip enabled us to de-risk backside power for our leading process nodes, placing Intel a node ahead of competitors in bringing backside power delivery to market.”

Sell said that PowerVia marks Intel’s return to innovative and execution leadership. Intel has stumbled in recent years, falling behind rival Advanced Micro Devices in chip design and trailing TSMC in chip manufacturing. Intel CEO Pat Gelsinger has pledged to get the company back on track with technology for its U.S. chipmaking factories.

Sell said that the company’s engineers have developed and proved the world’s first backside power
solution, taking a major step to the “angstrom era” of chipmaking. That means that the dimensions within chips are approaching an angstrom, or one ten-billionths of a meter.

Many in the industry have worried about the end of Moore’s Law, or the prediction made in the 1960s by the late Intel chairman emeritus Gordon Moore, who guessed that the number of transistors on a chip would double every couple of years. But an advance like PowerVia means progress is still possible.

Turning chipmaking upside down

PowerVia is actually about turning things upside down by running power through the backside of a chip. Intel says it’s a new approach to delivering power that required a radical rethink to both how chips are made and how they are tested.

For all the modern history of computer chips, they’ve been built like pizzas — from the bottom up, in
layers. In the case of chips, you start with the tiniest features, the transistors, and then you build up
increasingly less-tiny layers of wires that connect the transistors and different parts of the chip (these
are called interconnects), Sell said.

Included among those top layers are the wires that bring in the power that makes the chip function. When the chip is done, you flip it over, enclose it in packaging that provides connections to the outer
world, and you’re ready to put it in a computer.

But Intel said this approach is running into problems. As they get smaller and denser, the layers that
share interconnects and power connections have become an increasingly chaotic web that hinders the
overall performance of each chip.

Once an afterthought, “now they have a huge impact,” said Sell, who is part of the team that brought PowerVia to fruition. In short, power and signals fade, requiring workarounds or simply dumping more power in.

Two problems, one solution

Intel teams foresaw these issues — research and development on a new approach dates back a decade — nor does Intel face them alone. The solution that Intel and leading-edge chipmakers are all working toward is called “backside power,” to find a way to move the power wires below the transistor to the “back” side of the chip and thus leave the interconnect or “front” side cleanly focused only on interconnection.

Intel never took this approach before because the old way was more straightforward to make and, as noted, mostly wasn’t an issue. Intel is releasing two new papers about PowerVia the 2023 VLSI Symposium show in Kyoto, Japan. They note how Intel devised a process to manufacture it, test it and demonstrate positive performance results. The “test it” part is most important, but the manufacturing part is what’s most surprising. Throw out pizza making. For the first time, chipmaking is going two-sided.

Staying on the path

Intel has a long track record of introducing the industry’s most critical new technologies, such as strained silicon, Hi-K metal gate and FinFET, to propel Moore’s Law forward.

“We introduced it, and the industry followed,” Sell said.

With PowerVia and RibbonFET gate-all-around technology coming in 2024, Intel continues to lead the industry in chip design and process innovations, the company said.

PowerVia is the first to solve the growing interconnect bottleneck issue for chip designers. Surging use cases, including artificial intelligence and graphics, require smaller, denser and more powerful transistors to meet ever-growing computing demands.

How it works

Transistors are built first, as before, with the interconnect layers added next. Now the fun part: flip over the wafer and “polish everything off,” Sell said, to expose the bottom layer to which the wires (metal layers, as these “wires” are microscopic) for power will be connected.

“We call it silicon technology,” Sell said. “but the amount of silicon that’s left on these wafers is really
tiny.”

After the polish, “Now you only have very few metal layers and they’re all very thick,” Sell said. This “thick” refers to layers that are mere micrometers. That leaves “a very direct path for the power delivery to your transistor,” Sell said.

Cost, performance and power benefits outstrip complexity

Today and for the past many decades, power and signal lines within a transistor’s architecture have competed for the same resources.

By separating the two, chips can increase performance and energy-efficiency, and deliver better results for customers. Backside power delivery is vital to transistor scaling, enabling chip designers to increase transistor density without sacrificing resources to deliver more power and performance than ever.

“This stack of wiring gets really high. And as you scale the transistors to make them smaller and more powerful, all the wires, especially these lower wires, have to scale more and more and they become more and more of a bottleneck to computing,” Sell said. “Backside power delivery is taking all of these power wires from the front side and just moves them to the backside of that silicon.”

The benefits of this approach are numerous, Sell confirmed, surpassing the added complexity of the new
process.

The wires for power, for example, can take up to 20% of that front-side real estate, so with them gone, the interconnect layers can be “relaxed.” “That more than offsets the cost of this whole big process,” Sell said, simplifying what had been the most tortuous portion of the manufacturing flow. The net
effect is that the two-part, flip-it-over process is actually cheaper than the old way.

The benefits aren’t limited to manufacturing. The test chip the Intel team used to prove out the approach — called Blue Sky Creek and based on the E-core coming in Intel’s forthcoming Meteor Lake processor for PCs — demonstrated that PowerVia solved both problems caused by the old pizza method.

With separated and fatter wires for power and interconnection, “you get better power delivery and you get better signal wiring,” Sell said.

For your average computer user, this means more efficient speed. Get work done faster and with less power, the promise of Moore’s Law delivered again. As the second paper dryly concludes, “The Intel E-
core designed with PowerVia demonstrates greater than 5% frequency improvement and greater than 90% cell density with acceptable debug times as Intel 4.”

Sell confirms this is a “substantial” frequency boost for just moving wires around.

A unique test chip with intentional, hidden bugs

The last part of that conclusion — “acceptable debug times” — is a critical achievement alongside the
product improvements, Intel said. Today, chip testing techniques are based on the accessibility of the transistors in that first and lowest layer. With the transistors now sandwiched in the middle of the chip, “a lot of those techniques had to be redeveloped,” said Sell.

“There were a lot of concerns and hesitancy and that was probably the hardest thing to figure out —
how to do debug on this new backside power delivery,” Sell said.

To make things more challenging, the test chip design team intentionally added some “Easter egg” errors to the chip, unbeknownst to the validation team. The good news was they found the bugs.

“We have made tremendous progress over the last couple of years in developing those debug capabilities and proving them on Blue Sky Creek,” Sell said.

That brings up one more novel thing about how Sell and the Intel team figured out the PowerVia recipe. PowerVia will be introduced into Intel-manufactured silicon starting with the Intel 20A node, which enters production in 2024 (Intel 20A will also see the introduction of a new gate-all-around transistor design called RibbonFET; customers of Intel Foundry Services can benefit from both innovations in the subsequent Intel 18A node, arriving later in 2024).

To isolate the development of PowerVia, they took the well-proven transistors from the preceding Intel 4 process node and built a special in-between node with the power and interconnect design planned for Intel 20A. …and a special test process node to isolate backside power.

And while Intel manufacturing and design teams regularly create all manner of Frankenstein test-chips — to test new designs and IPs and to solidify silicon processes — they don’t usually make them as functional and complete as Blue Sky Creek. In this case, the teams needed to verify not only that they could build and test a chip this way, but also that the new configuration wouldn’t bring new issues into the final product.

For instance, heat problems change.

“Normally you use the silicon side also for heat dissipation,” Sell said. “So now you have sandwiched your transistors and the question is, ‘Do we have a thermal problem? Do we get a lot of local heating?’” Luckily, the answer is no.

“What was most amazing,” Sell said. “Despite these radical changes” — sandwiching transistors in the middle of the chip and introducing this heavy “polishing” to the process — “we could make the transistors look very, very close to what we had in Intel 4.”

As for PowerVia, it has no peer, INtel asserted. According to recent reports, Intel’s planned 2024 introduction of PowerVia would put competitors “roughly two years behind” when it comes to backside power.

“At least for this time period,” confirmed Sell, “we have a quite competitive backside power delivery
option.”

PowerVia’s first chip will come in the form of Arrow Lake, a next-generation Intel processor for PCs built using the Intel 20A process. Its billions of transistors will be inverted, working more efficiently than ever before, Intel said.

Originally appeared on: TheSpuzz